From 36ae6cb908875f9f952cb67f85397be6efaf8eb5 Mon Sep 17 00:00:00 2001 From: David Bandeira Date: Sat, 17 May 2025 11:10:39 +0200 Subject: [PATCH] sorting c64 folder / adding 4464 tester --- .../DRAM_Tester/DRAM_Tester-cache.lib | 298 ++ .../DRAM_Tester/DRAM_Tester.kicad_pcb | 1665 +++++++++ .../DRAM_Tester/DRAM_Tester.net | 446 +++ .../DRAM_Tester/DRAM_Tester.pro | 63 + .../DRAM_Tester/DRAM_Tester.rules | 78 + .../DRAM_Tester/DRAM_Tester.sch | 573 ++++ .../DRAM_Tester/Gerber/DRAM_Tester-B.Cu.gbr | 3009 +++++++++++++++++ .../DRAM_Tester/Gerber/DRAM_Tester-B.Mask.gbr | 163 + .../Gerber/DRAM_Tester-Edge.Cuts.gbr | 22 + .../DRAM_Tester/Gerber/DRAM_Tester-F.Cu.gbr | 2634 +++++++++++++++ .../DRAM_Tester/Gerber/DRAM_Tester-F.Mask.gbr | 163 + .../Gerber/DRAM_Tester-F.SilkS.gbr | 1302 +++++++ .../DRAM_Tester/Gerber/DRAM_Tester-drl.rpt | 27 + .../Gerber/DRAM_Tester-drl_map.gbr | 2276 +++++++++++++ .../DRAM_Tester/Gerber/DRAM_Tester.drl | 141 + .../DRAM_Testers/DRAM_Testers.ino | 183 + dram.tester/C64/DRAM_Tester-master/LICENSE | 674 ++++ dram.tester/C64/DRAM_Tester-master/README.md | 14 + dram.tester/C64/README.md | 6 + .../arduino_dram4164_tester-main/README.md | 0 .../dramtester/dramtester.ino | 0 dram.tester/README.md | 8 +- 22 files changed, 13739 insertions(+), 6 deletions(-) create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester-cache.lib create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.kicad_pcb create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.net create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.pro create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.rules create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.sch create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-B.Cu.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-B.Mask.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-Edge.Cuts.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-F.Cu.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-F.Mask.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-F.SilkS.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl.rpt create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl_map.gbr create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester.drl create mode 100644 dram.tester/C64/DRAM_Tester-master/DRAM_Testers/DRAM_Testers.ino create mode 100644 dram.tester/C64/DRAM_Tester-master/LICENSE create mode 100644 dram.tester/C64/DRAM_Tester-master/README.md create mode 100644 dram.tester/C64/README.md rename dram.tester/{ => C64}/arduino_dram4164_tester-main/README.md (100%) rename dram.tester/{ => C64}/arduino_dram4164_tester-main/dramtester/dramtester.ino (100%) diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester-cache.lib b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester-cache.lib new file mode 100644 index 0000000..cd7a465 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester-cache.lib @@ -0,0 +1,298 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# +5V +# +DEF +5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+5V" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# 4464 +# +DEF 4464 U 0 40 Y Y 1 F N +F0 "U" 150 550 60 H V C CNN +F1 "4464" -150 550 60 H V C CNN +F2 "" 0 -500 60 H I C CNN +F3 "" 0 -500 60 H I C CNN +DRAW +S -250 500 250 -500 0 1 0 N +X /OE 1 -450 400 200 R 50 50 1 1 I +X D0 2 -450 300 200 R 50 50 1 1 I +X D1 3 -450 200 200 R 50 50 1 1 I +X /WE 4 -450 100 200 R 50 50 1 1 I +X /RAS 5 -450 0 200 R 50 50 1 1 I +X A6 6 -450 -100 200 R 50 50 1 1 I +X A5 7 -450 -200 200 R 50 50 1 1 I +X A4 8 -450 -300 200 R 50 50 1 1 I +X VCC 9 -450 -400 200 R 50 50 1 1 I +X A7 10 450 -400 200 L 50 50 1 1 I +X A0 11 450 -300 200 L 50 50 1 1 I +X A1 12 450 -200 200 L 50 50 1 1 I +X A2 13 450 -100 200 L 50 50 1 1 I +X A3 14 450 0 200 L 50 50 1 1 I +X D2 15 450 100 200 L 50 50 1 1 I +X CAS 16 450 200 200 L 50 50 1 1 I +X D3 17 450 300 200 L 50 50 1 1 I +X GND 18 450 400 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# CONN_01X02 +# +DEF CONN_01X02 J 0 40 Y N 1 F N +F0 "J" 0 150 50 H V C CNN +F1 "CONN_01X02" 100 0 50 V V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + Pin_Header_Straight_1X* + Pin_Header_Angled_1X* + Socket_Strip_Straight_1X* + Socket_Strip_Angled_1X* +$ENDFPLIST +DRAW +S -50 -45 10 -55 0 1 0 N +S -50 55 10 45 0 1 0 N +S -50 100 50 -100 0 1 0 N +X P1 1 -200 50 150 R 50 50 1 1 P +X P2 2 -200 -50 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# KM44256 +# +DEF KM44256 U 0 20 Y Y 1 F N +F0 "U" 0 600 60 H V C CNN +F1 "KM44256" 0 700 60 H V C CNN +F2 "" 0 600 60 H I C CNN +F3 "" 0 600 60 H I C CNN +DRAW +S -250 500 250 -500 0 1 0 N +X D0 1 -450 450 200 R 50 50 1 1 I +X D1 2 -450 350 200 R 50 50 1 1 I +X /WE 3 -450 250 200 R 50 50 1 1 I +X /RAS 4 -450 150 200 R 50 50 1 1 I +X NC 5 -450 50 200 R 50 50 1 1 I +X A0 6 -450 -50 200 R 50 50 1 1 I +X A1 7 -450 -150 200 R 50 50 1 1 I +X A2 8 -450 -250 200 R 50 50 1 1 I +X A3 9 -450 -350 200 R 50 50 1 1 I +X VCC 10 -450 -450 200 R 50 50 1 1 I +X GND 20 450 450 200 L 50 50 1 1 I +X A4 11 450 -450 200 L 50 50 1 1 I +X A5 12 450 -350 200 L 50 50 1 1 I +X A6 13 450 -250 200 L 50 50 1 1 I +X A7 14 450 -150 200 L 50 50 1 1 I +X A8 15 450 -50 200 L 50 50 1 1 I +X /OE 16 450 50 200 L 50 50 1 1 I +X /CAS 17 450 150 200 L 50 50 1 1 I +X D2 18 450 250 200 L 50 50 1 1 I +X D3 19 450 350 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# LED +# +DEF LED D 0 40 Y N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "LED" 0 -100 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + LED* +$ENDFPLIST +DRAW +P 2 0 1 8 -50 -50 -50 50 N +P 2 0 1 0 -50 0 50 0 N +P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N +P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N +P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nano +# +DEF Nano U 0 30 Y Y 1 F N +F0 "U" 150 800 60 H V C CNN +F1 "Nano" -50 800 60 H V C CNN +F2 "" 50 -550 60 H I C CNN +F3 "" 50 -550 60 H I C CNN +DRAW +S -200 750 200 -750 0 1 0 N +X TX 1 -400 700 200 R 50 50 1 1 B +X RX 2 -400 600 200 R 50 50 1 1 B +X RST 3 -400 500 200 R 50 50 1 1 B +X GND 4 -400 400 200 R 50 50 1 1 B +X D2 5 -400 300 200 R 50 50 1 1 B +X D3 6 -400 200 200 R 50 50 1 1 B +X D4 7 -400 100 200 R 50 50 1 1 B +X D5 8 -400 0 200 R 50 50 1 1 B +X D6 9 -400 -100 200 R 50 50 1 1 B +X D7 10 -400 -200 200 R 50 50 1 1 B +X A1 20 400 -300 200 L 50 50 1 1 B +X VIN 30 400 700 200 L 50 50 1 1 B +X D8 11 -400 -300 200 R 50 50 1 1 B +X A2 21 400 -200 200 L 50 50 1 1 B +X D9 12 -400 -400 200 R 50 50 1 1 B +X A3 22 400 -100 200 L 50 50 1 1 B +X D10 13 -400 -500 200 R 50 50 1 1 B +X A4 23 400 0 200 L 50 50 1 1 B +X D11 14 -400 -600 200 R 50 50 1 1 B +X A5 24 400 100 200 L 50 50 1 1 B +X D12 15 -400 -700 200 R 50 50 1 1 B +X A6 25 400 200 200 L 50 50 1 1 B +X D13 16 400 -700 200 L 50 50 1 1 B +X A7 26 400 300 200 L 50 50 1 1 B +X 3V3 17 400 -600 200 L 50 50 1 1 B +X 5V 27 400 400 200 L 50 50 1 1 B +X REF 18 400 -500 200 L 50 50 1 1 B +X RST 28 400 500 200 L 50 50 1 1 B +X A0 19 400 -400 200 L 50 50 1 1 B +X GND 29 400 600 200 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# ProMini +# +DEF ProMini U 0 40 Y Y 1 F N +F0 "U" 0 -150 60 H V C CNN +F1 "ProMini" 0 -50 60 H V C CNN +F2 "" -500 -150 60 H I C CNN +F3 "" -500 -150 60 H I C CNN +DRAW +S -500 600 500 -600 0 1 0 N +X TX 1 -700 550 200 R 50 50 1 1 B +X RX 2 -700 450 200 R 50 50 1 1 B +X RST 3 -700 350 200 R 50 50 1 1 I +X GND 4 -700 250 200 R 50 50 1 1 W +X D2 5 -700 150 200 R 50 50 1 1 B +X D3 6 -700 50 200 R 50 50 1 1 B +X D4 7 -700 -50 200 R 50 50 1 1 B +X D5 8 -700 -150 200 R 50 50 1 1 B +X D6 9 -700 -250 200 R 50 50 1 1 B +X D7 10 -700 -350 200 R 50 50 1 1 B +X A3 20 700 150 200 L 50 50 1 1 B +X DTR 30 -250 800 200 D 50 50 1 1 B +X D8 11 -700 -450 200 R 50 50 1 1 B +X VCC 21 700 250 200 L 50 50 1 1 W +X TX 31 -150 800 200 D 50 50 1 1 B +X D9 12 -700 -550 200 R 50 50 1 1 B +X RST 22 700 350 200 L 50 50 1 1 I +X RX 32 -50 800 200 D 50 50 1 1 B +X D10 13 700 -550 200 L 50 50 1 1 B +X GND 23 700 450 200 L 50 50 1 1 W +X VCC 33 50 800 200 D 50 50 1 1 W +X D11 14 700 -450 200 L 50 50 1 1 B +X RAW 24 700 550 200 L 50 50 1 1 W +X GND 34 150 800 200 D 50 50 1 1 W +X D12 15 700 -350 200 L 50 50 1 1 B +X GND 25 -200 -800 200 U 50 50 1 1 W +X GND 35 250 800 200 D 50 50 1 1 W +X D13 16 700 -250 200 L 50 50 1 1 B +X A4 26 -100 -800 200 U 50 50 1 1 B +X A5' 36 250 200 200 L 50 50 1 1 B +X A0 17 700 -150 200 L 50 50 1 1 B +X A5/GND 27 0 -800 200 U 50 50 1 1 B +X A4' 37 250 100 200 L 50 50 1 1 B +X A1 18 700 -50 200 L 50 50 1 1 B +X A6 28 100 -800 200 U 50 50 1 1 B +X A2 19 700 50 200 L 50 50 1 1 B +X A7 29 200 -800 200 U 50 50 1 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 50 V I C CNN +F3 "" 0 0 50 H I C CNN +$FPLIST + R_* + R_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SW_SPDT +# +DEF SW_SPDT SW 0 3 Y Y 1 F N +F0 "SW" 0 400 60 H V C CNN +F1 "SW_SPDT" 0 300 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C -150 -150 50 0 1 0 N +C -150 150 50 0 1 0 N +C 150 0 50 0 1 0 N +S -200 200 200 -200 0 1 0 N +P 2 0 1 0 150 0 -150 150 N +X P1 1 -400 50 200 R 50 50 1 1 I +X COMM 2 400 -100 200 L 50 50 1 1 I +X P2 3 -400 -50 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# USB_B +# +DEF USB_B J 0 40 Y Y 1 F N +F0 "J" -200 450 50 H V L CNN +F1 "USB_B" -200 350 50 H V L CNN +F2 "" 150 -50 50 H I C CNN +F3 "" 150 -50 50 H I C CNN +$FPLIST + USB* +$ENDFPLIST +DRAW +C -150 85 25 0 1 10 F +C -25 135 15 0 1 10 F +S -200 -300 200 300 0 1 10 f +S -150 220 -100 180 0 1 0 F +S -5 -300 5 -270 0 1 0 N +S 10 50 -20 20 0 1 10 F +S 200 -105 170 -95 0 1 0 N +S 200 -5 170 5 0 1 0 N +S 200 195 170 205 0 1 0 N +P 2 0 1 10 -75 85 25 85 N +P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N +P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N +P 4 0 1 10 25 110 25 60 75 85 25 110 F +P 7 0 1 0 -160 170 -90 170 -90 225 -105 240 -145 240 -160 225 -160 170 N +X VBUS 1 300 200 100 L 50 50 1 1 w +X D- 2 300 -100 100 L 50 50 1 1 P +X D+ 3 300 0 100 L 50 50 1 1 P +X GND 4 0 -400 100 U 50 50 1 1 w +X Shield 5 -100 -400 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.kicad_pcb b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.kicad_pcb new file mode 100644 index 0000000..a5b4001 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.kicad_pcb @@ -0,0 +1,1665 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.6) + + (general + (links 77) + (no_connects 0) + (area 103.395 84.256999 169.007001 141.237001) + (thickness 1.6) + (drawings 8) + (tracks 398) + (zones 0) + (modules 11) + (nets 25) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal hide) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements 7FFFFFFF) + (pcbplotparams + (layerselection 0x010e0_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory Gerber/)) + ) + + (net 0 "") + (net 1 GND) + (net 2 "Net-(D1-Pad2)") + (net 3 "Net-(D2-Pad2)") + (net 4 R-LED) + (net 5 G-LED) + (net 6 +5V) + (net 7 SW) + (net 8 A6) + (net 9 A7) + (net 10 D0) + (net 11 A8) + (net 12 D1) + (net 13 D2) + (net 14 D3) + (net 15 CAS) + (net 16 RAS) + (net 17 WE) + (net 18 A0) + (net 19 A1) + (net 20 A2) + (net 21 A3) + (net 22 A4) + (net 23 A5) + (net 24 "Net-(J2-Pad5)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +5V) + (add_net A0) + (add_net A1) + (add_net A2) + (add_net A3) + (add_net A4) + (add_net A5) + (add_net A6) + (add_net A7) + (add_net A8) + (add_net CAS) + (add_net D0) + (add_net D1) + (add_net D2) + (add_net D3) + (add_net G-LED) + (add_net GND) + (add_net "Net-(D1-Pad2)") + (add_net "Net-(D2-Pad2)") + (add_net "Net-(J2-Pad5)") + (add_net R-LED) + (add_net RAS) + (add_net SW) + (add_net WE) + ) + + (module Connectors:USB_B (layer F.Cu) (tedit 5C971AC5) (tstamp 5C9716FB) + (at 155.702 125.762 270) + (descr "USB B connector") + (tags "USB_B USB_DEV") + (path /5C971484) + (fp_text reference J2 (at 5.81 1.27 360) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value USB_B (at 7.08 1.016 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 15.25 8.9) (end -2.3 8.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.3 8.9) (end -2.3 -6.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.3 -6.35) (end 15.25 -6.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 15.25 -6.35) (end 15.25 8.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start 6.35 7.37) (end 14.99 7.37) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.03 7.37) (end 3.05 7.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.35 -4.83) (end 14.99 -4.83) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.03 -4.83) (end 3.05 -4.83) (layer F.SilkS) (width 0.12)) + (fp_line (start 14.99 -4.83) (end 14.99 7.37) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.03 7.37) (end -2.03 -4.83) (layer F.SilkS) (width 0.12)) + (pad 2 thru_hole circle (at 0 2.54 180) (size 1.52 1.52) (drill 0.81) (layers *.Cu *.Mask)) + (pad 1 thru_hole circle (at 0 0 180) (size 1.52 1.52) (drill 0.81) (layers *.Cu *.Mask) + (net 6 +5V)) + (pad 4 thru_hole circle (at 2 0 180) (size 1.52 1.52) (drill 0.81) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 3 thru_hole circle (at 2 2.54 180) (size 1.52 1.52) (drill 0.81) (layers *.Cu *.Mask)) + (pad 5 thru_hole circle (at 4.7 7.27 180) (size 2.7 2.7) (drill 2.3) (layers *.Cu *.Mask) + (net 24 "Net-(J2-Pad5)")) + (pad 5 thru_hole circle (at 4.7 -4.73 180) (size 2.7 2.7) (drill 2.3) (layers *.Cu *.Mask) + (net 24 "Net-(J2-Pad5)")) + (model ${KISYS3DMOD}/Connectors.3dshapes/USB_B.wrl + (at (xyz 0.18 -0.05 0)) + (scale (xyz 0.39 0.39 0.39)) + (rotate (xyz 0 0 -90)) + ) + ) + + (module Modules:Arduino_Nano (layer F.Cu) (tedit 5CA5EBB7) (tstamp 5C924B02) + (at 111.76 90.932) + (descr "Arduino Nano, http://www.mouser.com/pdfdocs/Gravitech_Arduino_Nano3_0.pdf") + (tags "Arduino Nano") + (path /5C923C5E) + (fp_text reference U1 (at 7.62 -5.08) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Nano (at 17.78 -1.524 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 7.62 -5.08 180) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.27 -1.27) (end -1.4 -1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 1.27) (end -1.4 39.5) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.4 -3.94) (end -1.4 -1.27) (layer F.SilkS) (width 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length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf") + (tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 10.16mm 0.25W = 1/4W length 6.3mm diameter 2.5mm") + (path /5C924A48) + (fp_text reference R2 (at 5.08 -2.31 270) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 330 (at 5.08 0 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.93 -1.25) (end 1.93 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 1.93 1.25) (end 8.23 1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 1.25) (end 8.23 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 8.23 -1.25) (end 1.93 -1.25) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 1.93 0) (layer F.Fab) (width 0.1)) + (fp_line (start 10.16 0) (end 8.23 0) (layer F.Fab) (width 0.1)) + (fp_line (start 1.87 -1.31) (end 1.87 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.87 1.31) (end 8.29 1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 1.31) (end 8.29 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.29 -1.31) (end 1.87 -1.31) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.98 0) (end 1.87 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 9.18 0) (end 8.29 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.05 -1.6) (end -1.05 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 1.6) (end 11.25 1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 1.6) (end 11.25 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 11.25 -1.6) (end -1.05 -1.6) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole circle (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 3 "Net-(D2-Pad2)")) + (pad 2 thru_hole oval (at 10.16 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 5 G-LED)) + (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x03_Pitch2.54mm (layer F.Cu) (tedit 5C9717DC) (tstamp 5C924AE0) + (at 137.922 129.032 90) + (descr "Through hole straight socket strip, 1x03, 2.54mm pitch, single row") + (tags "Through hole socket strip THT 1x03 2.54mm single row") + (path /5C923E04) + (fp_text reference SW1 (at 0 -2.33 90) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value SW_SPDT (at -2.794 2.54 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.27 -1.27) (end -1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 6.35) (end 1.27 6.35) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 6.35) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 1.27) (end -1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 6.41) (end 1.33 6.41) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 6.41) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end -1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 6.85) (end 1.8 6.85) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 6.85) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2.33 90) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 +5V)) + (pad 2 thru_hole oval (at 0 2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 7 SW)) + (pad 3 thru_hole oval (at 0 5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Socket_Strips.3dshapes/Socket_Strip_Straight_1x03_Pitch2.54mm.wrl + (at (xyz 0 -0.1 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 270)) + ) + ) + + (module Housings_DIP:DIP-18_W7.62mm_Socket (layer F.Cu) (tedit 5C924DA2) (tstamp 5C924B18) + (at 157.48 87.884) + (descr "18-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils), Socket") + (tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil Socket") + (path /5C923EF9) + (fp_text reference U2 (at 3.81 -2.33) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 4464 (at 3.81 10.668 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 6.985 -1.27) (end 6.985 21.59) (layer F.Fab) (width 0.1)) + (fp_line (start 6.985 21.59) (end 0.635 21.59) (layer F.Fab) (width 0.1)) + (fp_line (start 0.635 21.59) (end 0.635 -0.27) (layer F.Fab) (width 0.1)) + (fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -1.33) (end -1.27 21.65) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 21.65) (end 8.89 21.65) (layer F.Fab) (width 0.1)) + (fp_line (start 8.89 21.65) (end 8.89 -1.33) (layer F.Fab) (width 0.1)) + (fp_line (start 8.89 -1.33) (end -1.27 -1.33) (layer F.Fab) (width 0.1)) + (fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.16 -1.33) (end 1.16 21.65) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.16 21.65) (end 6.46 21.65) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.46 21.65) (end 6.46 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.39) (end -1.33 21.71) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 21.71) (end 8.95 21.71) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.95 21.71) (end 8.95 -1.39) (layer F.SilkS) (width 0.12)) + (fp_line (start 8.95 -1.39) (end -1.33 -1.39) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.55 -1.6) (end -1.55 21.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 21.9) (end 9.15 21.9) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.15 21.9) (end 9.15 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.15 -1.6) (end -1.55 -1.6) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 3.81 10.16) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 10 thru_hole oval (at 7.62 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 9 A7)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 10 D0)) + (pad 11 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 18 A0)) + (pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 12 D1)) + (pad 12 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 19 A1)) + (pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 17 WE)) + (pad 13 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 20 A2)) + (pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 16 RAS)) + (pad 14 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 21 A3)) + (pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 8 A6)) + (pad 15 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 13 D2)) + (pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 23 A5)) + (pad 16 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 15 CAS)) + (pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 22 A4)) + (pad 17 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 14 D3)) + (pad 9 thru_hole oval (at 0 20.32) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 6 +5V)) + (pad 18 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Housings_DIP.3dshapes/DIP-18_W7.62mm_Socket.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module LEDs:LED_Rectangular_W5.0mm_H2.0mm (layer F.Cu) (tedit 5CA5F217) (tstamp 5C9716EB) + (at 107.188 111.252 270) + (descr "LED_Rectangular, Rectangular, Rectangular size 5.0x2.0mm^2, 2 pins, http://www.kingbright.com/attachments/file/psearch/000/00/00/L-169XCGDK(Ver.9B).pdf") + (tags "LED_Rectangular Rectangular Rectangular size 5.0x2.0mm^2 2 pins") + (path /5C924AFC) + (fp_text reference D2 (at 1.27 -2.06 270) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value ACTION/OK (at 1.27 2.06 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.23 -1) (end -1.23 1) (layer F.Fab) (width 0.1)) + (fp_line (start -1.23 1) (end 3.77 1) (layer F.Fab) (width 0.1)) + (fp_line (start 3.77 1) (end 3.77 -1) (layer F.Fab) (width 0.1)) + (fp_line (start 3.77 -1) (end -1.23 -1) (layer F.Fab) (width 0.1)) + (fp_line (start -1.29 -1.06) (end -1.08 -1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.08 -1.06) (end 1.811 -1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.27 -1.06) (end 3.83 -1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.29 1.06) (end -1.08 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.08 1.06) (end 1.811 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.27 1.06) (end 3.83 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.29 -1.06) (end -1.29 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.83 -1.06) (end 3.83 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.17 -1.06) (end -1.17 1.06) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.55 -1.35) (end -1.55 1.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 1.35) (end 4.1 1.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 1.35) (end 4.1 -1.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.1 -1.35) (end -1.55 -1.35) (layer F.CrtYd) (width 0.05)) + (pad 1 thru_hole rect (at 0 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 2 thru_hole circle (at 2.54 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask) + (net 3 "Net-(D2-Pad2)")) + (model ${KISYS3DMOD}/LEDs.3dshapes/LED_Rectangular_W5.0mm_H2.0mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 0.393701 0.393701 0.393701)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm (layer F.Cu) (tedit 5C9717F4) (tstamp 5C9716F1) + (at 164.592 126.492) + (descr "Through hole straight pin header, 1x02, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x02 2.54mm single row") + (path /5C9713E7) + (fp_text reference J1 (at 0 -2.54) (layer F.SilkS) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X02 (at 2.54 1.27 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 -1.27) (end 1.27 3.81) (layer F.Fab) (width 0.1)) + (fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 3.81) (end -1.27 -0.635) (layer F.Fab) (width 0.1)) + (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1)) + (fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end -1.33 3.87) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.33 1.27) (end 1.33 3.87) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.8 -1.8) (end -1.8 4.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.8 4.35) (end 1.8 4.35) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 4.35) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 -2.54) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 6 +5V)) + (pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask) + (net 1 GND)) + (model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x02_Pitch2.54mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Library:Arduino_Pro_Mini (layer F.Cu) (tedit 5CA5EE94) (tstamp 5CA5F6D5) + (at 124.968 115.316 270) + (path /5CA5F938) + (fp_text reference U4 (at -16.27 0 360) (layer F.SilkS) + (effects (font (size 1.2 1.2) (thickness 0.15))) + ) + (fp_text value ProMini (at 0 0 270) (layer F.Fab) + (effects (font (size 1.2 1.2) (thickness 0.15))) + ) + (fp_line (start -15.07 9.12) (end 15.07 9.12) (layer F.SilkS) (width 0.15)) + (fp_line (start 15.07 9.12) (end 15.07 -9.12) (layer F.SilkS) (width 0.15)) + (fp_line (start 15.07 -9.12) (end -15.07 -9.12) (layer F.SilkS) (width 0.15)) + (fp_line (start -15.07 -9.12) (end -15.07 -3.04) (layer F.SilkS) (width 0.15)) + (fp_line (start -15.07 -3.04) (end -14.62 -3.04) (layer F.SilkS) (width 0.15)) + (fp_line (start -14.62 -3.04) (end -14.62 3.039999) (layer F.SilkS) (width 0.15)) + (fp_line (start -14.62 3.039999) (end -15.07 3.039999) (layer F.SilkS) (width 0.15)) + (fp_line (start -15.07 3.039999) (end -15.07 9.12) (layer F.SilkS) (width 0.15)) + (pad 24 thru_hole oval (at -13.97 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask)) + (pad 1 thru_hole oval (at -13.97 7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask)) + (pad 23 thru_hole oval (at -11.43 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 2 thru_hole oval (at -11.43 7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask)) + (pad 22 thru_hole oval (at -8.89 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask)) + (pad 3 thru_hole oval (at -8.89 7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask)) + (pad 21 thru_hole oval (at -6.35 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 6 +5V)) + (pad 4 thru_hole oval (at -6.35 7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 1 GND)) + (pad 20 thru_hole oval (at -3.81 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 5 G-LED)) + (pad 5 thru_hole oval (at -3.81 7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 10 D0)) + (pad 19 thru_hole oval (at -1.27 -7.62 270) (size 1.2 2) (drill 0.8) (layers *.Cu *.Mask) + (net 11 A8)) + (pad 6 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(xy 141.694761 98.721552) (xy 141.448199 98.886299) (xy 140.751777 99.582721) + (xy 140.742811 99.569302) (xy 140.360725 99.314) (xy 140.742811 99.058698) (xy 141.05388 98.593151) (xy 141.163113 98.044) + (xy 141.05388 97.494849) (xy 140.742811 97.029302) (xy 140.360725 96.774) (xy 140.742811 96.518698) (xy 140.751777 96.505279) + ) + ) + ) +) diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.net b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.net new file mode 100644 index 0000000..8e7015f --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.net @@ -0,0 +1,446 @@ +(export (version D) + (design + (source D:\Work\KiCad\DRAM_Tester\DRAM_Tester.sch) + (date "2019-04-04 오후 8:59:38") + (tool "Eeschema 4.0.6") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source DRAM_Tester.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref U1) + (value Nano) + (footprint Modules:Arduino_Nano) + (libsource (lib cloudree_arduino) (part Nano)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C923C5E)) + (comp (ref SW1) + (value SW_SPDT) + (footprint Socket_Strips:Socket_Strip_Straight_1x03_Pitch2.54mm) + (libsource (lib cloudree_switch) (part SW_SPDT)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C923E04)) + (comp (ref U2) + (value 4464) + (footprint Housings_DIP:DIP-18_W7.62mm_Socket) + (libsource (lib cloudree_memory) (part 4464)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C923EF9)) + (comp (ref U3) + (value KM44256) + (footprint Housings_DIP:DIP-20_W7.62mm_Socket) + (libsource (lib cloudree_memory) (part KM44256)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C9245BD)) + (comp (ref R1) + (value 330) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C924A23)) + (comp (ref R2) + (value 330) + (footprint Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal) + (libsource (lib device) (part R)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C924A48)) + (comp (ref D1) + (value LED) + (footprint LEDs:LED_Rectangular_W5.0mm_H2.0mm) + (libsource (lib device) (part LED)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C924A99)) + (comp (ref D2) + (value LED) + (footprint LEDs:LED_Rectangular_W5.0mm_H2.0mm) + (libsource (lib device) (part LED)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C924AFC)) + (comp (ref J1) + (value CONN_01X02) + (footprint Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm) + (libsource (lib conn) (part CONN_01X02)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C9713E7)) + (comp (ref J2) + (value USB_B) + (footprint Connectors:USB_B) + (libsource (lib conn) (part USB_B)) + (sheetpath (names /) (tstamps /)) + (tstamp 5C971484)) + (comp (ref U4) + (value ProMini) + (footprint Library:Arduino_Pro_Mini) + (libsource (lib cloudree_arduino) (part ProMini)) + (sheetpath (names /) (tstamps /)) + (tstamp 5CA5F938))) + (libparts + (libpart (lib cloudree_memory) (part 4464) + (fields + (field (name Reference) U) + (field (name Value) 4464)) + (pins + (pin (num 1) (name /OE) (type input)) + (pin (num 2) (name D0) (type input)) + (pin (num 3) (name D1) (type input)) + (pin (num 4) (name /WE) (type input)) + (pin (num 5) (name /RAS) (type input)) + (pin (num 6) (name A6) (type input)) + (pin (num 7) (name A5) (type input)) + (pin (num 8) (name A4) (type input)) + (pin (num 9) (name VCC) (type input)) + (pin (num 10) (name A7) (type input)) + (pin (num 11) (name A0) (type input)) + (pin (num 12) (name A1) (type input)) + (pin (num 13) (name A2) (type input)) + (pin (num 14) (name A3) (type input)) + (pin (num 15) (name D2) (type input)) + (pin (num 16) (name CAS) (type input)) + (pin (num 17) (name D3) (type input)) + (pin (num 18) (name GND) (type input)))) + (libpart (lib conn) (part CONN_01X02) + (description "Connector, single row, 01x02, pin header") + (footprints + (fp Pin_Header_Straight_1X*) + (fp Pin_Header_Angled_1X*) + (fp Socket_Strip_Straight_1X*) + (fp Socket_Strip_Angled_1X*)) + (fields + (field (name Reference) J) + (field (name Value) CONN_01X02)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)))) + (libpart (lib cloudree_memory) (part KM44256) + (fields + (field (name Reference) U) + (field (name Value) KM44256)) + (pins + (pin (num 1) (name D0) (type input)) + (pin (num 2) (name D1) (type input)) + (pin (num 3) (name /WE) (type input)) + (pin (num 4) (name /RAS) (type input)) + (pin (num 5) (name NC) (type input)) + (pin (num 6) (name A0) (type input)) + (pin (num 7) (name A1) (type input)) + (pin (num 8) (name A2) (type input)) + (pin (num 9) (name A3) (type input)) + (pin (num 10) (name VCC) (type input)) + (pin (num 11) (name A4) (type input)) + (pin (num 12) (name A5) (type input)) + (pin (num 13) (name A6) (type input)) + (pin (num 14) (name A7) (type input)) + (pin (num 15) (name A8) (type input)) + (pin (num 16) (name /OE) (type input)) + (pin (num 17) (name /CAS) (type input)) + (pin (num 18) (name D2) (type input)) + (pin (num 19) (name D3) (type input)) + (pin (num 20) (name GND) (type input)))) + (libpart (lib device) (part LED) + (description "LED generic") + (footprints + (fp LED*)) + (fields + (field (name Reference) D) + (field (name Value) LED)) + (pins + (pin (num 1) (name K) (type passive)) + (pin (num 2) (name A) (type passive)))) + (libpart (lib cloudree_arduino) (part Nano) + (fields + (field (name Reference) U) + (field (name Value) Nano)) + (pins + (pin (num 1) (name TX) (type BiDi)) + (pin (num 2) (name RX) (type BiDi)) + (pin (num 3) (name RST) (type BiDi)) + (pin (num 4) (name GND) (type BiDi)) + (pin (num 5) (name D2) (type BiDi)) + (pin (num 6) (name D3) (type BiDi)) + (pin (num 7) (name D4) (type BiDi)) + (pin (num 8) (name D5) (type BiDi)) + (pin (num 9) (name D6) (type BiDi)) + (pin (num 10) (name D7) (type BiDi)) + (pin (num 11) (name D8) (type BiDi)) + (pin (num 12) (name D9) (type BiDi)) + (pin (num 13) (name D10) (type BiDi)) + (pin (num 14) (name D11) (type BiDi)) + (pin (num 15) (name D12) (type BiDi)) + (pin (num 16) (name D13) (type BiDi)) + (pin (num 17) (name 3V3) (type BiDi)) + (pin (num 18) (name REF) (type BiDi)) + (pin (num 19) (name A0) (type BiDi)) + (pin (num 20) (name A1) (type BiDi)) + (pin (num 21) (name A2) (type BiDi)) + (pin (num 22) (name A3) (type BiDi)) + (pin (num 23) (name A4) (type BiDi)) + (pin (num 24) (name A5) (type BiDi)) + (pin (num 25) (name A6) (type BiDi)) + (pin (num 26) (name A7) (type BiDi)) + (pin (num 27) (name 5V) (type BiDi)) + (pin (num 28) (name RST) (type BiDi)) + (pin (num 29) (name GND) (type BiDi)) + (pin (num 30) (name VIN) (type BiDi)))) + (libpart (lib cloudree_arduino) (part ProMini) + (fields + (field (name Reference) U) + (field (name Value) ProMini)) + (pins + (pin (num 1) (name TX) (type BiDi)) + (pin (num 2) (name RX) (type BiDi)) + (pin (num 3) (name RST) (type input)) + (pin (num 4) (name GND) (type power_in)) + (pin (num 5) (name D2) (type BiDi)) + (pin (num 6) (name D3) (type BiDi)) + (pin (num 7) (name D4) (type BiDi)) + (pin (num 8) (name D5) (type BiDi)) + (pin (num 9) (name D6) (type BiDi)) + (pin (num 10) (name D7) (type BiDi)) + (pin (num 11) (name D8) (type BiDi)) + (pin (num 12) (name D9) (type BiDi)) + (pin (num 13) (name D10) (type BiDi)) + (pin (num 14) (name D11) (type BiDi)) + (pin (num 15) (name D12) (type BiDi)) + (pin (num 16) (name D13) (type BiDi)) + (pin (num 17) (name A0) (type BiDi)) + (pin (num 18) (name A1) (type BiDi)) + (pin (num 19) (name A2) (type BiDi)) + (pin (num 20) (name A3) (type BiDi)) + (pin (num 21) (name VCC) (type power_in)) + (pin (num 22) (name RST) (type input)) + (pin (num 23) (name GND) (type power_in)) + (pin (num 24) (name RAW) (type power_in)) + (pin (num 25) (name GND) (type power_in)) + (pin (num 26) (name A4) (type BiDi)) + (pin (num 27) (name A5/GND) (type BiDi)) + (pin (num 28) (name A6) (type BiDi)) + (pin (num 29) (name A7) (type BiDi)) + (pin (num 30) (name DTR) (type BiDi)) + (pin (num 31) (name TX) (type BiDi)) + (pin (num 32) (name RX) (type BiDi)) + (pin (num 33) (name VCC) (type power_in)) + (pin (num 34) (name GND) (type power_in)) + (pin (num 35) (name GND) (type power_in)) + (pin (num 36) (name A5') (type BiDi)) + (pin (num 37) (name A4') (type BiDi)))) + (libpart (lib device) (part R) + (description Resistor) + (footprints + (fp R_*) + (fp R_*)) + (fields + (field (name Reference) R) + (field (name Value) R)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib cloudree_switch) (part SW_SPDT) + (fields + (field (name Reference) SW) + (field (name Value) SW_SPDT)) + (pins + (pin (num 1) (name P1) (type input)) + (pin (num 2) (name COMM) (type input)) + (pin (num 3) (name P2) (type input)))) + (libpart (lib conn) (part USB_B) + (description "USB Type B connector") + (footprints + (fp USB*)) + (fields + (field (name Reference) J) + (field (name Value) USB_B)) + (pins + (pin (num 1) (name VBUS) (type power_out)) + (pin (num 2) (name D-) (type passive)) + (pin (num 3) (name D+) (type passive)) + (pin (num 4) (name GND) (type power_out)) + (pin (num 5) (name Shield) (type passive))))) + (libraries + (library (logical conn) + (uri D:\Programs\KiCad\share\kicad\library\conn.lib)) + (library (logical device) + (uri D:\Programs\KiCad\share\kicad\library\device.lib)) + (library (logical cloudree_switch) + (uri D:\Work\KiCad\cloudree_switch.lib)) + (library (logical cloudree_arduino) + (uri D:\Work\KiCad\cloudree_arduino.lib)) + (library (logical cloudree_memory) + (uri D:\Work\KiCad\cloudree_memory.lib))) + (nets + (net (code 1) (name "Net-(U4-Pad33)") + (node (ref U4) (pin 33))) + (net (code 2) (name GND) + (node (ref U2) (pin 18)) + (node (ref U2) (pin 1)) + (node (ref U4) (pin 25)) + (node (ref U1) (pin 29)) + (node (ref U3) (pin 20)) + (node (ref U3) (pin 16)) + (node (ref D1) (pin 1)) + (node (ref U4) (pin 23)) + (node (ref U4) (pin 4)) + (node (ref D2) (pin 1)) + (node (ref J1) (pin 2)) + (node (ref J2) (pin 4)) + (node (ref SW1) (pin 3)) + (node (ref U1) (pin 4))) + (net (code 3) (name "Net-(U4-Pad24)") + (node (ref U4) (pin 24))) + (net (code 4) (name "Net-(U4-Pad22)") + (node (ref U4) (pin 22))) + (net (code 5) (name "Net-(U4-Pad3)") + (node (ref U4) (pin 3))) + (net (code 6) (name "Net-(U4-Pad2)") + (node (ref U4) (pin 2))) + (net (code 7) (name "Net-(U4-Pad1)") + (node (ref U4) (pin 1))) + (net (code 8) (name "Net-(U4-Pad35)") + (node (ref U4) (pin 35))) + (net (code 9) (name "Net-(U4-Pad34)") + (node (ref U4) (pin 34))) + (net (code 10) (name "Net-(U4-Pad32)") + (node (ref U4) (pin 32))) + (net (code 11) (name "Net-(U4-Pad31)") + (node (ref U4) (pin 31))) + (net (code 12) (name "Net-(U4-Pad30)") + (node (ref U4) (pin 30))) + (net (code 13) (name G-LED) + (node (ref U4) (pin 20)) + (node (ref R2) (pin 2)) + (node (ref U1) (pin 22))) + (net (code 14) (name R-LED) + (node (ref U4) (pin 36)) + (node (ref U4) (pin 27)) + (node (ref U1) (pin 24)) + (node (ref R1) (pin 2))) + (net (code 15) (name +5V) + (node (ref U3) (pin 10)) + (node (ref U1) (pin 27)) + (node (ref J2) (pin 1)) + (node (ref SW1) (pin 1)) + (node (ref J1) (pin 1)) + (node (ref U2) (pin 9)) + (node (ref U4) (pin 21))) + (net (code 16) (name "Net-(U3-Pad5)") + (node (ref U3) (pin 5))) + (net (code 17) (name "Net-(D1-Pad2)") + (node (ref R1) (pin 1)) + (node (ref D1) (pin 2))) + (net (code 18) (name "Net-(D2-Pad2)") + (node (ref D2) (pin 2)) + (node (ref R2) (pin 1))) + (net (code 19) (name A2) + (node (ref U1) (pin 13)) + (node (ref U3) (pin 8)) + (node (ref U4) (pin 13)) + (node (ref U2) (pin 13))) + (net (code 20) (name A1) + (node (ref U2) (pin 12)) + (node (ref U4) (pin 12)) + (node (ref U3) (pin 7)) + (node (ref U1) (pin 12))) + (net (code 21) (name A0) + (node (ref U3) (pin 6)) + (node (ref U1) (pin 11)) + (node (ref U2) (pin 11)) + (node (ref U4) (pin 11))) + (net (code 22) (name WE) + (node (ref U1) (pin 10)) + (node (ref U3) (pin 3)) + (node (ref U2) (pin 4)) + (node (ref U4) (pin 10))) + (net (code 23) (name RAS) + (node (ref U1) (pin 9)) + (node (ref U3) (pin 4)) + (node (ref U2) (pin 5)) + (node (ref U4) (pin 9))) + (net (code 24) (name CAS) + (node (ref U1) (pin 8)) + (node (ref U4) (pin 8)) + (node (ref U2) (pin 16)) + (node (ref U3) (pin 17))) + (net (code 25) (name D2) + (node (ref U3) (pin 18)) + (node (ref U1) (pin 7)) + (node (ref U2) (pin 15)) + (node (ref U4) (pin 7))) + (net (code 26) (name "Net-(U4-Pad29)") + (node (ref U4) (pin 29))) + (net (code 27) (name SW) + (node (ref SW1) (pin 2)) + (node (ref U1) (pin 25)) + (node (ref U4) (pin 28))) + (net (code 28) (name D1) + (node (ref U4) (pin 6)) + (node (ref U3) (pin 2)) + (node (ref U2) (pin 3)) + (node (ref U1) (pin 6))) + (net (code 29) (name D3) + (node (ref U4) (pin 37)) + (node (ref U3) (pin 19)) + (node (ref U4) (pin 26)) + (node (ref U1) (pin 23)) + (node (ref U2) (pin 17))) + (net (code 30) (name "Net-(J2-Pad2)") + (node (ref J2) (pin 2))) + (net (code 31) (name "Net-(J2-Pad3)") + (node (ref J2) (pin 3))) + (net (code 32) (name "Net-(J2-Pad5)") + (node (ref J2) (pin 5))) + (net (code 33) (name D0) + (node (ref U1) (pin 5)) + (node (ref U2) (pin 2)) + (node (ref U3) (pin 1)) + (node (ref U4) (pin 5))) + (net (code 34) (name "Net-(U1-Pad17)") + (node (ref U1) (pin 17))) + (net (code 35) (name "Net-(U1-Pad18)") + (node (ref U1) (pin 18))) + (net (code 36) (name "Net-(U1-Pad28)") + (node (ref U1) (pin 28))) + (net (code 37) (name "Net-(U1-Pad26)") + (node (ref U1) (pin 26))) + (net (code 38) (name "Net-(U1-Pad30)") + (node (ref U1) (pin 30))) + (net (code 39) (name "Net-(U1-Pad3)") + (node (ref U1) (pin 3))) + (net (code 40) (name "Net-(U1-Pad2)") + (node (ref U1) (pin 2))) + (net (code 41) (name "Net-(U1-Pad1)") + (node (ref U1) (pin 1))) + (net (code 42) (name A3) + (node (ref U4) (pin 14)) + (node (ref U2) (pin 14)) + (node (ref U1) (pin 14)) + (node (ref U3) (pin 9))) + (net (code 43) (name A4) + (node (ref U4) (pin 15)) + (node (ref U2) (pin 8)) + (node (ref U3) (pin 11)) + (node (ref U1) (pin 15))) + (net (code 44) (name A5) + (node (ref U4) (pin 16)) + (node (ref U1) (pin 16)) + (node (ref U2) (pin 7)) + (node (ref U3) (pin 12))) + (net (code 45) (name A6) + (node (ref U4) (pin 17)) + (node (ref U3) (pin 13)) + (node (ref U1) (pin 19)) + (node (ref U2) (pin 6))) + (net (code 46) (name A7) + (node (ref U1) (pin 20)) + (node (ref U3) (pin 14)) + (node (ref U2) (pin 10)) + (node (ref U4) (pin 18))) + (net (code 47) (name A8) + (node (ref U1) (pin 21)) + (node (ref U4) (pin 19)) + (node (ref U3) (pin 15))))) \ No newline at end of file diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.pro b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.pro new file mode 100644 index 0000000..af23398 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.pro @@ -0,0 +1,63 @@ +update=2019-03-20 오후 10:19:40 +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=D:/Work/KiCad/cloudree_arduino +LibName31=D:/Work/KiCad/cloudree_memory +LibName32=D:/Work/KiCad/cloudree_switch diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.rules b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.rules new file mode 100644 index 0000000..b5461ac --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.rules @@ -0,0 +1,78 @@ + +(rules PCB DRAM_Tester + (snap_angle + fortyfive_degree + ) + (autoroute_settings + (fanout off) + (autoroute on) + (postroute on) + (vias on) + (via_costs 50) + (plane_via_costs 5) + (start_ripup_costs 100) + (start_pass_no 1802) + (layer_rule F.Cu + (active on) + (preferred_direction horizontal) + (preferred_direction_trace_costs 1.0) + (against_preferred_direction_trace_costs 2.3) + ) + (layer_rule B.Cu + (active on) + (preferred_direction vertical) + (preferred_direction_trace_costs 1.0) + (against_preferred_direction_trace_costs 1.8) + ) + ) + (rule + (width 250.0) + (clear 200.2) + (clear 125.0 (type smd_to_turn_gap)) + (clear 50.0 (type smd_smd)) + ) + (padstack "Via[0-1]_600:400_um" + (shape + (circle F.Cu 600.0 0.0 0.0) + ) + (shape + (circle B.Cu 600.0 0.0 0.0) + ) + (attach off) + ) + (via + "Via[0-1]_600:400_um" "Via[0-1]_600:400_um" default + ) + (via + "Via[0-1]_600:400_um-kicad_default" "Via[0-1]_600:400_um" "kicad_default" + ) + (via_rule + default "Via[0-1]_600:400_um" + ) + (via_rule + "kicad_default" "Via[0-1]_600:400_um-kicad_default" + ) + (class default + (clearance_class default) + (via_rule default) + (rule + (width 250.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) + (class "kicad_default" + GND "Net-(D1-Pad2)" "Net-(D2-Pad2)" "R-LED" "G-LED" +5V SW A6 + A7 D0 A8 D1 D2 D3 CAS RAS + WE A0 A1 A2 A3 A4 A5 "Net-(J2-Pad5)" + (clearance_class "kicad_default") + (via_rule kicad_default) + (rule + (width 250.0) + ) + (circuit + (use_layer F.Cu B.Cu) + ) + ) +) \ No newline at end of file diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.sch b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.sch new file mode 100644 index 0000000..6665a0e --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/DRAM_Tester.sch @@ -0,0 +1,573 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:cloudree_arduino +LIBS:cloudree_memory +LIBS:cloudree_switch +LIBS:DRAM_Tester-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Nano U1 +U 1 1 5C923C5E +P 4700 3850 +F 0 "U1" H 4850 4650 60 0000 C CNN +F 1 "Nano" H 4650 4650 60 0000 C CNN +F 2 "Modules:Arduino_Nano" H 4750 3300 60 0001 C CNN +F 3 "" H 4750 3300 60 0001 C CNN + 1 4700 3850 + 1 0 0 -1 +$EndComp +NoConn ~ 4300 3150 +NoConn ~ 4300 3250 +NoConn ~ 4300 3350 +NoConn ~ 5100 3150 +NoConn ~ 5100 3350 +NoConn ~ 5100 4350 +NoConn ~ 5100 4450 +$Comp +L GND #PWR01 +U 1 1 5C923D1C +P 4300 3450 +F 0 "#PWR01" H 4300 3200 50 0001 C CNN +F 1 "GND" H 4300 3300 50 0000 C CNN +F 2 "" H 4300 3450 50 0001 C CNN +F 3 "" H 4300 3450 50 0001 C CNN + 1 4300 3450 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5C923D31 +P 5100 3250 +F 0 "#PWR02" H 5100 3000 50 0001 C CNN +F 1 "GND" H 5100 3100 50 0000 C CNN +F 2 "" H 5100 3250 50 0001 C CNN +F 3 "" H 5100 3250 50 0001 C CNN + 1 5100 3250 + 0 -1 -1 0 +$EndComp +$Comp +L +5V #PWR03 +U 1 1 5C923D40 +P 5100 3450 +F 0 "#PWR03" H 5100 3300 50 0001 C CNN +F 1 "+5V" H 5100 3590 50 0000 C CNN +F 2 "" H 5100 3450 50 0001 C CNN +F 3 "" H 5100 3450 50 0001 C CNN + 1 5100 3450 + 0 1 1 0 +$EndComp +Text GLabel 4300 3950 0 60 Output ~ 0 +RAS +Text GLabel 4300 3850 0 60 Output ~ 0 +CAS +Text GLabel 4300 4050 0 60 Output ~ 0 +WE +Text GLabel 5100 3950 2 60 Output ~ 0 +G-LED +Text GLabel 5100 3750 2 60 Output ~ 0 +R-LED +Text GLabel 5100 3650 2 60 Input ~ 0 +SW +Text GLabel 4300 3550 0 60 BiDi ~ 0 +D0 +Text GLabel 4300 3650 0 60 BiDi ~ 0 +D1 +Text GLabel 5100 3850 2 60 BiDi ~ 0 +D3 +Text GLabel 4300 3750 0 60 BiDi ~ 0 +D2 +Text GLabel 4300 4150 0 60 Output ~ 0 +A0 +Text GLabel 4300 4250 0 60 Output ~ 0 +A1 +Text GLabel 4300 4350 0 60 Output ~ 0 +A2 +Text GLabel 4300 4450 0 60 Output ~ 0 +A3 +Text GLabel 4300 4550 0 60 Output ~ 0 +A4 +Text GLabel 5100 4550 2 60 Output ~ 0 +A5 +Text GLabel 5100 4250 2 60 Output ~ 0 +A6 +Text GLabel 5100 4150 2 60 Output ~ 0 +A7 +Text GLabel 5100 4050 2 60 Output ~ 0 +A8 +NoConn ~ 5100 3550 +$Comp +L SW_SPDT SW1 +U 1 1 5C923E04 +P 6300 3050 +F 0 "SW1" H 6300 3450 60 0000 C CNN +F 1 "SW_SPDT" H 6300 3350 60 0000 C CNN +F 2 "Socket_Strips:Socket_Strip_Straight_1x03_Pitch2.54mm" H 6300 3050 60 0001 C CNN +F 3 "" H 6300 3050 60 0001 C CNN + 1 6300 3050 + 1 0 0 -1 +$EndComp +Text GLabel 6700 3150 2 60 Output ~ 0 +SW +$Comp +L +5V #PWR04 +U 1 1 5C923EA3 +P 5900 3000 +F 0 "#PWR04" H 5900 2850 50 0001 C CNN +F 1 "+5V" H 5900 3140 50 0000 C CNN +F 2 "" H 5900 3000 50 0001 C CNN +F 3 "" H 5900 3000 50 0001 C CNN + 1 5900 3000 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR05 +U 1 1 5C923EBB +P 5900 3100 +F 0 "#PWR05" H 5900 2850 50 0001 C CNN +F 1 "GND" H 5900 2950 50 0000 C CNN +F 2 "" H 5900 3100 50 0001 C CNN +F 3 "" H 5900 3100 50 0001 C CNN + 1 5900 3100 + 0 1 1 0 +$EndComp +$Comp +L 4464 U2 +U 1 1 5C923EF9 +P 6300 4150 +F 0 "U2" H 6450 4700 60 0000 C CNN +F 1 "4464" H 6150 4700 60 0000 C CNN +F 2 "Housings_DIP:DIP-18_W7.62mm_Socket" H 6300 3650 60 0001 C CNN +F 3 "" H 6300 3650 60 0001 C CNN + 1 6300 4150 + 1 0 0 -1 +$EndComp +Text GLabel 5850 3850 0 60 BiDi ~ 0 +D0 +Text GLabel 5850 3950 0 60 BiDi ~ 0 +D1 +Text GLabel 5850 4250 0 60 Input ~ 0 +A6 +Text GLabel 5850 4350 0 60 Input ~ 0 +A5 +Text GLabel 5850 4450 0 60 Input ~ 0 +A4 +Text GLabel 6750 4550 2 60 Input ~ 0 +A7 +Text GLabel 6750 4450 2 60 Input ~ 0 +A0 +Text GLabel 6750 4350 2 60 Input ~ 0 +A1 +Text GLabel 6750 4250 2 60 Input ~ 0 +A2 +Text GLabel 6750 4150 2 60 Input ~ 0 +A3 +Text GLabel 6750 4050 2 60 BiDi ~ 0 +D2 +Text GLabel 6750 3850 2 60 BiDi ~ 0 +D3 +Text GLabel 6750 3950 2 60 Input ~ 0 +CAS +Text GLabel 5850 4050 0 60 Input ~ 0 +WE +Text GLabel 5850 4150 0 60 Input ~ 0 +RAS +$Comp +L GND #PWR06 +U 1 1 5C923FF0 +P 6750 3750 +F 0 "#PWR06" H 6750 3500 50 0001 C CNN +F 1 "GND" H 6750 3600 50 0000 C CNN +F 2 "" H 6750 3750 50 0001 C CNN +F 3 "" H 6750 3750 50 0001 C CNN + 1 6750 3750 + 0 -1 -1 0 +$EndComp +$Comp +L +5V #PWR07 +U 1 1 5C92400A +P 5850 4550 +F 0 "#PWR07" H 5850 4400 50 0001 C CNN +F 1 "+5V" H 5850 4690 50 0000 C CNN +F 2 "" H 5850 4550 50 0001 C CNN +F 3 "" H 5850 4550 50 0001 C CNN + 1 5850 4550 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR08 +U 1 1 5C924024 +P 5850 3750 +F 0 "#PWR08" H 5850 3500 50 0001 C CNN +F 1 "GND" H 5850 3600 50 0000 C CNN +F 2 "" H 5850 3750 50 0001 C CNN +F 3 "" H 5850 3750 50 0001 C CNN + 1 5850 3750 + 0 1 1 0 +$EndComp +$Comp +L KM44256 U3 +U 1 1 5C9245BD +P 8050 4150 +F 0 "U3" H 8050 4750 60 0000 C CNN +F 1 "KM44256" H 8050 4850 60 0000 C CNN +F 2 "Housings_DIP:DIP-20_W7.62mm_Socket" H 8050 4750 60 0001 C CNN +F 3 "" H 8050 4750 60 0001 C CNN + 1 8050 4150 + 1 0 0 -1 +$EndComp +Text GLabel 7600 3700 0 60 BiDi ~ 0 +D0 +Text GLabel 7600 3800 0 60 BiDi ~ 0 +D1 +Text GLabel 8500 3900 2 60 BiDi ~ 0 +D2 +Text GLabel 8500 3800 2 60 BiDi ~ 0 +D3 +Text GLabel 7600 3900 0 60 Input ~ 0 +WE +Text GLabel 7600 4000 0 60 Input ~ 0 +RAS +Text GLabel 7600 4200 0 60 Input ~ 0 +A0 +Text GLabel 7600 4300 0 60 Input ~ 0 +A1 +Text GLabel 7600 4400 0 60 Input ~ 0 +A2 +Text GLabel 7600 4500 0 60 Input ~ 0 +A3 +Text GLabel 8500 4200 2 60 Input ~ 0 +A8 +Text GLabel 8500 4300 2 60 Input ~ 0 +A7 +Text GLabel 8500 4400 2 60 Input ~ 0 +A6 +Text GLabel 8500 4500 2 60 Input ~ 0 +A5 +Text GLabel 8500 4600 2 60 Input ~ 0 +A4 +NoConn ~ 7600 4100 +Text GLabel 8500 4000 2 60 Input ~ 0 +CAS +$Comp +L GND #PWR09 +U 1 1 5C924779 +P 8500 3700 +F 0 "#PWR09" H 8500 3450 50 0001 C CNN +F 1 "GND" H 8500 3550 50 0000 C CNN +F 2 "" H 8500 3700 50 0001 C CNN +F 3 "" H 8500 3700 50 0001 C CNN + 1 8500 3700 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR010 +U 1 1 5C924795 +P 8500 4100 +F 0 "#PWR010" H 8500 3850 50 0001 C CNN +F 1 "GND" H 8500 3950 50 0000 C CNN +F 2 "" H 8500 4100 50 0001 C CNN +F 3 "" H 8500 4100 50 0001 C CNN + 1 8500 4100 + 0 -1 -1 0 +$EndComp +$Comp +L +5V #PWR011 +U 1 1 5C9247B1 +P 7600 4600 +F 0 "#PWR011" H 7600 4450 50 0001 C CNN +F 1 "+5V" H 7600 4740 50 0000 C CNN +F 2 "" H 7600 4600 50 0001 C CNN +F 3 "" H 7600 4600 50 0001 C CNN + 1 7600 4600 + 0 -1 -1 0 +$EndComp +$Comp +L R R1 +U 1 1 5C924A23 +P 7850 2950 +F 0 "R1" V 7930 2950 50 0000 C CNN +F 1 "330" V 7850 2950 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 7780 2950 50 0001 C CNN +F 3 "" H 7850 2950 50 0001 C CNN + 1 7850 2950 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5C924A48 +P 7850 3150 +F 0 "R2" V 7930 3150 50 0000 C CNN +F 1 "330" V 7850 3150 50 0000 C CNN +F 2 "Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 7780 3150 50 0001 C CNN +F 3 "" H 7850 3150 50 0001 C CNN + 1 7850 3150 + 0 1 1 0 +$EndComp +$Comp +L LED D1 +U 1 1 5C924A99 +P 8150 2950 +F 0 "D1" H 8150 3050 50 0000 C CNN +F 1 "LED" H 8150 2850 50 0000 C CNN +F 2 "LEDs:LED_Rectangular_W5.0mm_H2.0mm" H 8150 2950 50 0001 C CNN +F 3 "" H 8150 2950 50 0001 C CNN + 1 8150 2950 + -1 0 0 1 +$EndComp +$Comp +L LED D2 +U 1 1 5C924AFC +P 8150 3150 +F 0 "D2" H 8150 3250 50 0000 C CNN +F 1 "LED" H 8150 3050 50 0000 C CNN +F 2 "LEDs:LED_Rectangular_W5.0mm_H2.0mm" H 8150 3150 50 0001 C CNN +F 3 "" H 8150 3150 50 0001 C CNN + 1 8150 3150 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR012 +U 1 1 5C924B5B +P 8500 2950 +F 0 "#PWR012" H 8500 2700 50 0001 C CNN +F 1 "GND" H 8500 2800 50 0000 C CNN +F 2 "" H 8500 2950 50 0001 C CNN +F 3 "" H 8500 2950 50 0001 C CNN + 1 8500 2950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8500 2950 8300 2950 +Wire Wire Line + 8400 2950 8400 3150 +Wire Wire Line + 8400 3150 8300 3150 +Connection ~ 8400 2950 +Text GLabel 7600 2950 0 60 Input ~ 0 +R-LED +Text GLabel 7600 3150 0 60 Input ~ 0 +G-LED +Wire Wire Line + 7700 2950 7600 2950 +Wire Wire Line + 7600 3150 7700 3150 +NoConn ~ 4700 950 +NoConn ~ 4800 950 +NoConn ~ 4900 950 +NoConn ~ 5000 950 +NoConn ~ 5100 950 +NoConn ~ 5200 950 +NoConn ~ 4250 1200 +NoConn ~ 4250 1300 +NoConn ~ 4250 1400 +NoConn ~ 5650 1400 +NoConn ~ 5650 1200 +$Comp +L GND #PWR013 +U 1 1 5C970E6D +P 4250 1500 +F 0 "#PWR013" H 4250 1250 50 0001 C CNN +F 1 "GND" H 4250 1350 50 0000 C CNN +F 2 "" H 4250 1500 50 0001 C CNN +F 3 "" H 4250 1500 50 0001 C CNN + 1 4250 1500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR014 +U 1 1 5C970E93 +P 4750 2550 +F 0 "#PWR014" H 4750 2300 50 0001 C CNN +F 1 "GND" H 4750 2400 50 0000 C CNN +F 2 "" H 4750 2550 50 0001 C CNN +F 3 "" H 4750 2550 50 0001 C CNN + 1 4750 2550 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR015 +U 1 1 5C970EB9 +P 5650 1300 +F 0 "#PWR015" H 5650 1050 50 0001 C CNN +F 1 "GND" H 5650 1150 50 0000 C CNN +F 2 "" H 5650 1300 50 0001 C CNN +F 3 "" H 5650 1300 50 0001 C CNN + 1 5650 1300 + 0 -1 -1 0 +$EndComp +$Comp +L +5V #PWR016 +U 1 1 5C970EDF +P 5650 1500 +F 0 "#PWR016" H 5650 1350 50 0001 C CNN +F 1 "+5V" H 5650 1640 50 0000 C CNN +F 2 "" H 5650 1500 50 0001 C CNN +F 3 "" H 5650 1500 50 0001 C CNN + 1 5650 1500 + 0 1 1 0 +$EndComp +Text GLabel 4250 1600 0 60 BiDi ~ 0 +D0 +Text GLabel 4250 1700 0 60 BiDi ~ 0 +D1 +Text GLabel 4250 1800 0 60 BiDi ~ 0 +D2 +Text GLabel 4850 2550 3 60 BiDi ~ 0 +D3 +Text GLabel 4250 1900 0 60 Output ~ 0 +CAS +Text GLabel 4250 2000 0 60 Output ~ 0 +RAS +Text GLabel 4250 2100 0 60 Output ~ 0 +WE +Text GLabel 4250 2200 0 60 Output ~ 0 +A0 +Text GLabel 4250 2300 0 60 Output ~ 0 +A1 +Text GLabel 5650 2300 2 60 Output ~ 0 +A2 +Text GLabel 5650 2200 2 60 Output ~ 0 +A3 +Text GLabel 5650 2100 2 60 Output ~ 0 +A4 +Text GLabel 5650 2000 2 60 Output ~ 0 +A5 +Text GLabel 5650 1900 2 60 Output ~ 0 +A6 +Text GLabel 5650 1800 2 60 Output ~ 0 +A7 +Text GLabel 5650 1700 2 60 Output ~ 0 +A8 +Text GLabel 5650 1600 2 60 Output ~ 0 +G-LED +Text GLabel 4950 2550 3 60 Output ~ 0 +R-LED +Text GLabel 5050 2550 3 60 Input ~ 0 +SW +NoConn ~ 5150 2550 +$Comp +L CONN_01X02 J1 +U 1 1 5C9713E7 +P 6600 1300 +F 0 "J1" H 6600 1450 50 0000 C CNN +F 1 "CONN_01X02" V 6700 1300 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_1x02_Pitch2.54mm" H 6600 1300 50 0001 C CNN +F 3 "" H 6600 1300 50 0001 C CNN + 1 6600 1300 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR017 +U 1 1 5C971434 +P 6400 1250 +F 0 "#PWR017" H 6400 1100 50 0001 C CNN +F 1 "+5V" H 6400 1390 50 0000 C CNN +F 2 "" H 6400 1250 50 0001 C CNN +F 3 "" H 6400 1250 50 0001 C CNN + 1 6400 1250 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR018 +U 1 1 5C97145C +P 6400 1350 +F 0 "#PWR018" H 6400 1100 50 0001 C CNN +F 1 "GND" H 6400 1200 50 0000 C CNN +F 2 "" H 6400 1350 50 0001 C CNN +F 3 "" H 6400 1350 50 0001 C CNN + 1 6400 1350 + 1 0 0 -1 +$EndComp +$Comp +L USB_B J2 +U 1 1 5C971484 +P 7400 1600 +F 0 "J2" H 7200 2050 50 0000 L CNN +F 1 "USB_B" H 7200 1950 50 0000 L CNN +F 2 "Connectors:USB_B" H 7550 1550 50 0001 C CNN +F 3 "" H 7550 1550 50 0001 C CNN + 1 7400 1600 + 1 0 0 -1 +$EndComp +NoConn ~ 7700 1600 +NoConn ~ 7700 1700 +NoConn ~ 7300 2000 +$Comp +L GND #PWR019 +U 1 1 5C971553 +P 7400 2000 +F 0 "#PWR019" H 7400 1750 50 0001 C CNN +F 1 "GND" H 7400 1850 50 0000 C CNN +F 2 "" H 7400 2000 50 0001 C CNN +F 3 "" H 7400 2000 50 0001 C CNN + 1 7400 2000 + 1 0 0 -1 +$EndComp +$Comp +L +5V #PWR020 +U 1 1 5C97157D +P 7700 1400 +F 0 "#PWR020" H 7700 1250 50 0001 C CNN +F 1 "+5V" H 7700 1540 50 0000 C CNN +F 2 "" H 7700 1400 50 0001 C CNN +F 3 "" H 7700 1400 50 0001 C CNN + 1 7700 1400 + 1 0 0 -1 +$EndComp +$Comp +L ProMini U4 +U 1 1 5CA5F938 +P 4950 1750 +F 0 "U4" H 4950 1600 60 0000 C CNN +F 1 "ProMini" H 4950 1700 60 0000 C CNN +F 2 "Library:Arduino_Pro_Mini" H 4450 1600 60 0001 C CNN +F 3 "" H 4450 1600 60 0001 C CNN + 1 4950 1750 + 1 0 0 -1 +$EndComp +Text GLabel 5200 1550 2 60 Output ~ 0 +R-LED +Text GLabel 5200 1650 2 60 BiDi ~ 0 +D3 +$EndSCHEMATC diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-B.Cu.gbr b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-B.Cu.gbr new file mode 100644 index 0000000..4219fda --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-B.Cu.gbr @@ -0,0 +1,3009 @@ +G04 #@! TF.FileFunction,Copper,L2,Bot,Signal* +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 4.0.6) date 04/12/19 16:58:46* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%ADD10C,0.100000*% +%ADD11C,1.520000*% +%ADD12C,2.700000*% +%ADD13R,1.600000X1.600000*% +%ADD14O,1.600000X1.600000*% +%ADD15R,1.800000X1.800000*% +%ADD16C,1.800000*% +%ADD17C,1.600000*% +%ADD18R,1.700000X1.700000*% +%ADD19O,1.700000X1.700000*% +%ADD20O,2.000000X1.200000*% +%ADD21C,1.524000*% +%ADD22C,0.250000*% +%ADD23C,0.254000*% +G04 APERTURE END LIST* +D10* +D11* +X153162000Y-125762000D03* +X155702000Y-125762000D03* +X155702000Y-127762000D03* +X153162000Y-127762000D03* +D12* +X148432000Y-130462000D03* +X160432000Y-130462000D03* +D13* +X111760000Y-90932000D03* +D14* +X127000000Y-123952000D03* +X111760000Y-93472000D03* +X127000000Y-121412000D03* +X111760000Y-96012000D03* +X127000000Y-118872000D03* +X111760000Y-98552000D03* +X127000000Y-116332000D03* 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b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl.rpt new file mode 100644 index 0000000..2dbfade --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl.rpt @@ -0,0 +1,27 @@ +Drill report for D:\Work\KiCad\DRAM_Tester\DRAM_Tester.kicad_pcb +Created on 2019-04-12 오후 4:58:59 + +Copper Layer Stackup: + ============================================================= + L1 : F.Cu front + L2 : B.Cu back + + +Drill file 'DRAM_Tester.drl' contains + plated through holes: + ============================================================= + T1 0.76mm 0.030" (7 holes) + T2 0.80mm 0.031" (96 holes) + T3 0.81mm 0.032" (4 holes) + T4 0.90mm 0.035" (4 holes) + T5 1.00mm 0.039" (5 holes) + T6 2.30mm 0.091" (2 holes) + + Total plated holes count 118 + + +Drill file 'DRAM_Tester-NPTH.drl' contains + unplated through holes: + ============================================================= + + Total unplated holes count 0 diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl_map.gbr b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl_map.gbr new file mode 100644 index 0000000..15ab144 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Tester/Gerber/DRAM_Tester-drl_map.gbr @@ -0,0 +1,2276 @@ +%FSLAX45Y45*% +G04 Gerber Fmt 4.5, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 4.0.6) date 04/12/19 16:58:53* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +%ADD10C,0.127000*% +%ADD11C,0.150000*% +%ADD12C,0.200000*% +%ADD13C,0.300000*% +G04 APERTURE END LIST* +D10* +D11* +X16893200Y-13433200D02* +X10393200Y-13433200D01* +X16893200Y-8433200D02* +X16893200Y-13433200D01* +X10393200Y-8433200D02* +X10393200Y-13433200D01* +X10393200Y-8433200D02* +X16893200Y-8433200D01* +D12* +X11950700Y-12890500D02* +X12026900Y-12966700D01* +X12026900Y-12890500D02* +X11950700Y-12966700D01* +X12204700Y-12890500D02* +X12280900Y-12966700D01* +X12280900Y-12890500D02* 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+X107.188Y-113.792 +T5 +X137.922Y-129.032 +X140.462Y-129.032 +X143.002Y-129.032 +X164.592Y-126.492 +X164.592Y-129.032 +T6 +X148.432Y-130.462 +X160.432Y-130.462 +T0 +M30 diff --git a/dram.tester/C64/DRAM_Tester-master/DRAM_Testers/DRAM_Testers.ino b/dram.tester/C64/DRAM_Tester-master/DRAM_Testers/DRAM_Testers.ino new file mode 100644 index 0000000..fee2edd --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/DRAM_Testers/DRAM_Testers.ino @@ -0,0 +1,183 @@ +// +// DRAM_Testers for 4464, 44256 +// by cloudree@naver.com +// +// 4464 RAS CAS W D0 D1 D2 D3 A0 A1 A2 A3 A4 A5 A6 A7 +// 44256 RAS CAS W D0 D1 D2 D3 A0 A1 A2 A3 A4 A5 A6 A7 A8 G-LED R-LED SW +// Arduino D6 D5 D7 D2 D3 D4 A4 D8 D9 D10 D11 D12 D13 A0 A1 A2 A3 A5 A6 +// + +/* Simple DRAM tester + * Chris Osborn + * http://insentricity.com/a.cl/252 + */ + +#include + +#define _DEBUG +#define DATA_BITS 4 +#define MAX_ADDR_BITS 10 + +int DATA[ DATA_BITS ] = { 2, 3, 4, A4 }; + +#define CAS 5 +#define RAS 6 +#define WE 7 + +#define G_LED A3 +#define R_LED A5 +#define SW A6 + +bool g_is44256 = false; + +inline void writePrepare() +{ + for( int i = 0; i < DATA_BITS; i ++ ) + pinMode( DATA[i], OUTPUT ); +} + +inline void writeData( int value ) +{ + digitalWrite( DATA[0], value & 1 ); + digitalWrite( DATA[1], value & 2 ); + digitalWrite( DATA[2], value & 4 ); + digitalWrite( DATA[3], value & 8 ); +} + +inline void readPrepare() +{ + for( int i = 0; i < DATA_BITS; i ++ ) + pinMode( DATA[i], INPUT ); +} + +inline int readData() +{ + return digitalRead( DATA[0] ) + | ( digitalRead( DATA[1] ) << 1 ) + | ( digitalRead( DATA[2] ) << 2 ) + | ( digitalRead( DATA[3] ) << 3 ); +} + +inline int getAddrSize() +{ + return g_is44256 ? 10 : 8; +} + +inline void setAddress( int row, int col ) +{ + PORTB = row & 0x3f; + PORTC = (PORTC & 0xf0) | (row >> 6) & 0x0f; + digitalWrite(RAS, LOW); + digitalWrite(WE, LOW); + + PORTB = col & 0x3f; + PORTC = (PORTC & 0xf0) | (col >> 6) & 0x0f; + digitalWrite(CAS, LOW); + digitalWrite(WE, HIGH); + + digitalWrite(CAS, HIGH); + digitalWrite(RAS, HIGH); +} + +inline int getAddress( int row, int col ) +{ + PORTB = row & 0x3f; + PORTC = (PORTC & 0xf0) | (row >> 6) & 0x0f; + digitalWrite(RAS, LOW); + + PORTB = col & 0x3f; + PORTC = (PORTC & 0xf0) | (col >> 6) & 0x0f; + digitalWrite(CAS, LOW); + + int val = readData( ); + + digitalWrite(CAS, HIGH); + digitalWrite(RAS, HIGH); + + return val; +} + +void result( bool success ) +{ + digitalWrite( G_LED, success ? HIGH : LOW ); + digitalWrite( R_LED, success ? LOW : HIGH ); +#ifdef _DEBUG + Serial.println( success ? "\nSuccess" : "\nFailed" ); +#endif + while( 1 ) ; +} + +void setup() +{ +#ifdef _DEBUG + Serial.begin( 57600 ); + Serial.println( "DRAM Tester by cloudree@naver.com"); +#endif + + pinMode(CAS, OUTPUT); + pinMode(RAS, OUTPUT); + pinMode(WE, OUTPUT); + digitalWrite(CAS, HIGH); + digitalWrite(RAS, HIGH); + digitalWrite(WE, HIGH); + + /* 10 is max address bits, even if chip is smaller */ + int mask = (1 << MAX_ADDR_BITS) - 1; + DDRB = mask & 0x3f; + mask >>= 6; + DDRC = mask & 0x0f; + + pinMode( G_LED, OUTPUT ); + pinMode( R_LED, OUTPUT ); + digitalWrite( G_LED, LOW ); + digitalWrite( R_LED, LOW ); + + pinMode( SW, INPUT ); + g_is44256 = analogRead( SW ) > 500; + Serial.println( g_is44256 ? "Checking 44256" : "Checking 4464"); +} + +void loop() +{ + int count = 0; + byte vals[] = { 0x5, 0xa }; + + for( int col = 0; col < (1 << getAddrSize()); col ++ ) + { + for( int row = 0; row < (1 << getAddrSize()); row ++ ) + { + for( int idx = 0; idx < sizeof(vals); idx ++ ) + { + if ( millis() % 1000 > 500 ) digitalWrite( G_LED, HIGH ); + byte val = vals[idx]; + writePrepare(); + writeData( val ); + setAddress( row, col ); + writeData( ~val ); + digitalWrite( G_LED, LOW ); + + readPrepare(); + int ret = getAddress( row, col ); + if( ret != val ) + { +#ifdef _DEBUG + Serial.println( "Error, row=" + String(row) + ", col=" + String(col) + " : " + String(val) + "/" + String(ret) ); +#endif + result( false ); + } + } + } +#ifdef _DEBUG + Serial.print("."); +#endif + + if( ++count > 64 ) + { +#ifdef _DEBUG + Serial.println(""); +#endif + count = 0; + } + } + result( true ); +} diff --git a/dram.tester/C64/DRAM_Tester-master/LICENSE b/dram.tester/C64/DRAM_Tester-master/LICENSE new file mode 100644 index 0000000..f288702 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/dram.tester/C64/DRAM_Tester-master/README.md b/dram.tester/C64/DRAM_Tester-master/README.md new file mode 100644 index 0000000..35fbad1 --- /dev/null +++ b/dram.tester/C64/DRAM_Tester-master/README.md @@ -0,0 +1,14 @@ +# DRAM_Tester +44256 / 4464 Dram Tester with Arduino + +DRAM_Tester folder : KiCAD schematics and gerber files for arduino nano (or pro-mini) + +DRAM_Testers : Arduino source + +my blog posting (korean) : + +https://blog.naver.com/cloudree/221388540394 + +https://blog.naver.com/cloudree/221524164049 + +Good Luck! diff --git a/dram.tester/C64/README.md b/dram.tester/C64/README.md new file mode 100644 index 0000000..6d8cf10 --- /dev/null +++ b/dram.tester/C64/README.md @@ -0,0 +1,6 @@ +# dram.tester/C64 +## Propose: Testing C64 DRAMs +### Dram 4164 1x 65536 bit (8 x 8 KB IC Chips / Long Board) +Based on Git Project: https://github.com/randyrossi/arduino_dram4164_tester +### Dram 4464 4x 65536 bit (2 x 32 KB IC Chips / Short Board) +Based on Git Project: https://github.com/cloudree/DRAM_Tester diff --git a/dram.tester/arduino_dram4164_tester-main/README.md b/dram.tester/C64/arduino_dram4164_tester-main/README.md similarity index 100% rename from dram.tester/arduino_dram4164_tester-main/README.md rename to dram.tester/C64/arduino_dram4164_tester-main/README.md diff --git a/dram.tester/arduino_dram4164_tester-main/dramtester/dramtester.ino b/dram.tester/C64/arduino_dram4164_tester-main/dramtester/dramtester.ino similarity index 100% rename from dram.tester/arduino_dram4164_tester-main/dramtester/dramtester.ino rename to dram.tester/C64/arduino_dram4164_tester-main/dramtester/dramtester.ino diff --git a/dram.tester/README.md b/dram.tester/README.md index 98c2fab..d8f4731 100644 --- a/dram.tester/README.md +++ b/dram.tester/README.md @@ -1,6 +1,2 @@ -# dram.tester -## Propose: Test of old C64 OLD DRAM Modules 4164 and 4464 -### Dram 4164 1x 65536 bit (8 x 8 KB IC Chips / Long Board) -Based on Git Project: https://github.com/randyrossi/arduino_dram4164_tester -### Dram 4464 4x 65536 bit (2 x 32 KB IC Chips / Short Board) -Based on Git Project: https://github.com/cloudree/DRAM_Tester \ No newline at end of file +# dram.tester/C64 +## Propose: Test of old C64 OLD DRAM Modules 4164 and 4464 \ No newline at end of file